Exemplary embodiments relate to a semiconductor memory device and a method of operating the same and, more particularly, to a semiconductor memory device and a method of operating the same, which are capable of optimizing operating conditions.
A semiconductor memory device receives and stores data. In nonvolatile memory devices, such as flash memory, data is stored through a program operation, data is deleted through an erase operation, and data is outputted through a read operation.
In the flash memory device, the threshold voltage level of a memory cell is shifted according to data stored in the memory cell. That is, the threshold voltage of a memory cell is shifted through a program operation or an erase operation. In order to check whether the threshold voltage of the memory cell has shifted to a target voltage, a program verification operation or an erase verification operation is performed.
In a common flash memory device, when a bit line is precharged to a first voltage and a verification voltage is supplied to the gate of a memory cell coupled to the bit line, voltage of the bit line remains intact or shifts according to the difference between the verification voltage and a threshold voltage of the memory cell. The threshold voltage of the memory cell can be checked based on a change in the voltage of the bit line. The threshold voltage of the memory cell is checked based on a sensing current level detected in a program verification operation performed after a program operation and detected in an erase verification operation performed after an erase operation.
After the erase operation, the threshold voltage level of a memory cell becomes lower than 0 V. In the erase verification operation, the threshold voltage level of the memory cell that is sensed should be lower than 0 V.
Unlike in a program verification operation, in an erase verification operation, the threshold voltages of memory cells coupled to a bit line are sensed by supplying the same erase verification voltage to all the gates of the memory cells. Here, the erase verification voltage supplied to the gates is lower than a read pass voltage which is supplied to the gates of unselected memory cells when a read operation is performed on memory cells on which a program operation has been performed. Accordingly, an actually sensed threshold voltage is lower than the voltage supplied to the gates. This is called a back pattern dependency (BPD) effect. Consequently, a threshold voltage of a negative potential can be sensed even without using a negative voltage.
Meanwhile, with an increase in the number of program and erase cycles, the influence of current degradation is increased and so an erase verification level gradually shows a downward tendency. When the erase verification level gradually falls, the level of an erase voltage supplied for the erase operation gradually rises, and the electrical properties of a memory cell are deteriorated.
Furthermore, with an increase in the number of program and erase cycles, a threshold voltage level shifts according to the level of a sensing current. Accordingly, the level of an erase voltage supplied during the erase operation is influenced.